Added automatic dependency system to Makefile.

Makefile

@@ -1,10 +1,11 @@
 # Declaration of variables
 C = clang
-C_FLAGS = -Wall
+COMMON_FLAGS = -Wall -MMD
+C_FLAGS = $(COMMON_FLAGS)
 CC = clang++
-CC_FLAGS = -Wall -std=c++17
-LD_FLAGS = 
-INCLUDES = 
+CC_FLAGS = $(COMMON_FLAGS) -std=c++17
+LD_FLAGS =
+INCLUDES =
 
 # File names
 EXEC = run
@@ -12,22 +13,25 @@ CSOURCES = $(wildcard *.c)
 COBJECTS = $(CSOURCES:.c=.o)
 SOURCES = $(wildcard *.cpp)
 OBJECTS = $(SOURCES:.cpp=.o)
- 
+
 # Main target
 $(EXEC): $(COBJECTS) $(OBJECTS)
-	$(CC) $(LD_FLAGS) $(COBJECTS) $(OBJECTS) -o $(EXEC)
- 
+	$(CC) $(COBJECTS) $(OBJECTS) -o $(EXEC) $(LD_FLAGS)
+
 # To obtain object files
 %.o: %.cpp
 	$(CC) $(INCLUDES) $(CC_FLAGS) -o $@ -c $<
- 
+
 # To obtain object files
 %.o: %.c
 	$(C) $(INCLUDES) $(C_FLAGS) -o $@ -c $<
- 
+
+-include $(SOURCES:%.cpp=%.d)
+-include $(CSOURCES:%.c=%.d)
+
 # To remove generated files
 clean:
-	rm -f $(COBJECTS) $(OBJECTS)
+	rm -f $(COBJECTS) $(OBJECTS) $(SOURCES:%.cpp=%.d) $(CSOURCES:%.c=%.d)
 
-cleaner:
-	rm -f $(EXEC) $(COBJECTS) $(OBJECTS)
+cleaner: clean
+	rm -f $(EXEC)

main.cpp

@@ -8,8 +8,7 @@ using std::endl;
 
 int main()
 {
-	
+
 	
 	return 0;
 }
-

test_c_lib.c

@@ -0,0 +1 @@
+#include "test_c_lib.h"

test_c_lib.h

@@ -0,0 +1,6 @@
+#ifndef DEF_test_c_lib
+#define DEF_test_c_lib
+
+
+
+#endif